College/University/Organization
Name: Sri Ramakrishna Engineering College,
Coimbatore
Organizing Department: Department of Electronics and Communication Engineering (PG)
Event Date: 2015-09-08 -- 2015-09-09
(YYYY/MM/DD)
Last Date: 2015-08-26 (YYYY/MM/DD)
Address: Coimbatore , Tamilnadu , India
Registration Fee:
Research Scholars, UG/PG Students
& Faculty from Academic
Institutions : Rs 1000
Participants from Industry / R&D
organizations : Rs. 1500
IEEE Members (Proof for Membership) : Rs.750
Email Address: manikandababu.shelvaraju@srec.ac.in
About Event:
This workshop provides necessary skills to design advanced
system and debug using Vivado IP Integrator, Hardware Analyzer, Vivado HLS and
Partial Reconfiguration. The workshop, aims at:
Use Xilinx Design Constraints to communicate performance
Rapidly architect an embedded system targeting the ARM processor of Zynq.
Extend the hardware system with Xilinx provided peripherals
Create a custom peripheral and add it to the system
Debug a design using Vivado hardware analyzer
Use Vivado HLS to generate an IP-XACT compliant hardware accelerator
Design reconfigurable systems which using embedded processor in Zynq.
Use Xilinx Design Constraints to communicate performance
Rapidly architect an embedded system targeting the ARM processor of Zynq.
Extend the hardware system with Xilinx provided peripherals
Create a custom peripheral and add it to the system
Debug a design using Vivado hardware analyzer
Use Vivado HLS to generate an IP-XACT compliant hardware accelerator
Design reconfigurable systems which using embedded processor in Zynq.
Other Details:
Course Content
Day I:
Introduction - 7-Series Architecture Overview and Vivado Design Flow
Lab 1: Creating an HDL Design
o Use Vivado IDE to create a simple HDL design. Simulate the design using the XSIM HDL simulator available in Vivado design suite.
o Generate the bitstream and verify in hardware.
Xilinx Design Constraints
Lab 2: Xilinx Design Constraints
o Create a project with I/O Planning type, enter pin locations, and export it to the rtl. Thencreate the timing constraints and perform the timing analysis.
IP Integrator and Embedded System Design Flow
Lab 3: Create a Processor System using IP Integrator
o Create a simple ARM Cortex-A9 based processor design targeting the ZedBoard using IPIntegrator.
DayII:
Introduction to High-Level Synthesis with Vivado HLS
Improving Performance and Resource Utilization
Creating an Accelerator
Lab 4: Creating a Processor System using Accelerator
o Profile an application performing a function both in software and hardware. Create an accelerator in Vivado HLS. Use the generated accelerator to build a complete system.
Introduction to Partial Reconfiguration (PR)
Introduction to Vivado for PR Designs
Lab 5: Introduction to Partial Reconfiguration Design Flow
o Use Vivado with Partial Reconfiguration (PR) capability enabled to synthesize HDL models and implement the design.
Day I:
Introduction - 7-Series Architecture Overview and Vivado Design Flow
Lab 1: Creating an HDL Design
o Use Vivado IDE to create a simple HDL design. Simulate the design using the XSIM HDL simulator available in Vivado design suite.
o Generate the bitstream and verify in hardware.
Xilinx Design Constraints
Lab 2: Xilinx Design Constraints
o Create a project with I/O Planning type, enter pin locations, and export it to the rtl. Thencreate the timing constraints and perform the timing analysis.
IP Integrator and Embedded System Design Flow
Lab 3: Create a Processor System using IP Integrator
o Create a simple ARM Cortex-A9 based processor design targeting the ZedBoard using IPIntegrator.
DayII:
Introduction to High-Level Synthesis with Vivado HLS
Improving Performance and Resource Utilization
Creating an Accelerator
Lab 4: Creating a Processor System using Accelerator
o Profile an application performing a function both in software and hardware. Create an accelerator in Vivado HLS. Use the generated accelerator to build a complete system.
Introduction to Partial Reconfiguration (PR)
Introduction to Vivado for PR Designs
Lab 5: Introduction to Partial Reconfiguration Design Flow
o Use Vivado with Partial Reconfiguration (PR) capability enabled to synthesize HDL models and implement the design.
Contact Details:
The Convenor,
Department of ECE-PG,
Sri Ramakrishna Engineering College,
Coimbatore – 641 022.
Phone : 0422-2460088, 2461588
Mobile : 99941 58642, 94863 55965
Department of ECE-PG,
Sri Ramakrishna Engineering College,
Coimbatore – 641 022.
Phone : 0422-2460088, 2461588
Mobile : 99941 58642, 94863 55965
A Two Day
National Workshop on VLSI SYSTEM DESIGN
USING VIVADO & HLS-2015-Sri
Ramakrishna Engineering College, Coimbatore-641022.-Coimbatore -Tamilnadu
-India
See Also