College/University/Organization
Name: K S R INSTITUTE FOR ENGINEERING AND TECHNOLOGY
Organizing Department: ECE
Event Date: 03/18/2016 -- 03/18/2016
(MM/DD/YYYY)
Last Date: 03/16/2016 (MM/DD/YYYY)
Address: ERODE, NAMAKKAL, Tamilnadu, India
Registration Fee:
UG/PG Students - Rs.300
Faculty/Research Scholars - Rs.400
Industry Persons - Rs.400
Faculty/Research Scholars - Rs.400
Industry Persons - Rs.400
College/University/Organization
Website: www.ksriet.ac.in
Event Website / Brochure link: www.ksriet.ac.in
Email Address: ggowthamrajg@gmail.com
About Event:
This workshop has emphasis to provide a platform for interaction
and to discuss about the recent advances, new paradigms, technological trends
and challenges in the field of CMOS design and fabrication. Also this workshop
provides an excellent opportunity to exchange ideas on the topics of importance
along with thought provoking technical sessions like IC designs and EDA tools,
by eminent experts form EDA companies like Microwind.
COURSE CONTENT
COURSE CONTENT
CMOS Technology
Recent trends in VLSI Technology
Introduction to CMOS VLSI design and basics design techniques
Front end and Back end Design Techniques
Fabrication Techniques
Deep-Submicron CMOS cell design issues, introduction to 45 nanometer technology, strained silicon design, 45nm rules & characteristics, ASIC design flow using cell library & rule based design, timing issues, techniques for improving power consumption and speed, backend design issues & applications
Introduction to MICROWIND software & illustration of
design
Designing and analysis of basics of NMOS and PMOS transistors
Strong and Weak concept of transistor and Illustration of
why we prefer CMOS technology though we have NMOS
and PMOS?
Practical aspects
Full custom and Semi-custom Design of CMOS Inverter with Hands on session
W/L ratio and its importance and Sizing factor
Concept: Mobility principle
Electro migration principle
Why size of PMOS transistor is double than NMOS transistor?
Designing of universal gates and Analysis (Practical understanding. Why we prefer NAND gate instead of NOR?)
Practical session using schematic & layout Practical concepts, and experimentation Digital Design & Analysis
Assignment Session -Complex Inverter design
Designing of Digital and combinational logic designing
Physical layout designing concepts and analysis
Parametric analysis.
Actual implementation of active and passive components
in VLSI designs
Mixed signal simulation
Design of Differential oscillator and finding out
characteristics such as output impedance, CMRR and
Bandwidth
Who Can Participate?
2nd, 3rd and Final Year Students of ECE, or those who are
interested to learn VLSI back end design.
Accommodation Details:
Yes if requested in earlier
Other Details:
RESOURCE PERSON:
Mr. Shrikant R. Atkarne, Application Engineer (Microwind), ni logic Pvt. Ltd. (ni2designs), Pune.
Mr. Shrikant R. Atkarne, Application Engineer (Microwind), ni logic Pvt. Ltd. (ni2designs), Pune.
Contact Details:
Mr.G.Gowtham Raj
Coordinator, Department of ECE,
KSR Institute for Engineering and Technology,
Tiruchengode - 637215
Ph: 9444931347/8754960004
ggowthamrajg@gmail.com
Coordinator, Department of ECE,
KSR Institute for Engineering and Technology,
Tiruchengode - 637215
Ph: 9444931347/8754960004
ggowthamrajg@gmail.com
For any clarification about
this event, please contact the above mentioned address.
One day
National level Workshop on CMOS VLSI DESIGN USING MICROWIND AND DSCH-2016-K S R
INSTITUTE FOR ENGINEERING AND TECHNOLOGY-ERODE, NAMAKKAL-Tamilnadu-India
See Also