College/University/Organization
Name: Maven silicon Softech Pvt Ltd
Organizing Department: Electronics
Event Date: 09/03/2016 -- 09/04/2016
(MM/DD/YYYY)
Last Date: 08/15/2016 (MM/DD/YYYY)
Address: Bangalore, Karnataka, India
Registration Fee:
Registration
Registration Fee includes FDP Kit, Lunch & Refreshments and participation in all programmes related to the FDP.
The details of registration fee are as follows:
Early Bird Registration Registration
Rs. 3,000/- Rs. 5,000/-
Early Bird Offer applicable up-to 30th June,2016!
Kindly contact us for group discounts for 2 or more faculties joining from same college.
Registration Fee includes FDP Kit, Lunch & Refreshments and participation in all programmes related to the FDP.
The details of registration fee are as follows:
Early Bird Registration Registration
Rs. 3,000/- Rs. 5,000/-
Early Bird Offer applicable up-to 30th June,2016!
Kindly contact us for group discounts for 2 or more faculties joining from same college.
College/University/Organization
Website: http://www.maven-silicon.com
Event Website / Brochure link: http://goo.gl/forms/gmy0nwj2NWdEGETp2
Email Address: vimala@maven-silicon.com
About Event:
Invitation from Maven Silicon!!
Maven Silicon, Bangalore is organizing a Faculty Development Program (FDP) on “Functional Verification” in collaboration with Aceic Design Technologies on 3rd and 4th,September 2016.
This workshop will give the participants an invaluable resource for those who are trying to gain insight about the current needs in the VLSI industry with Key Sessions delivered by non other than Mr. Sivakumar PR- Founder and CEO of Aceic Design Technologies. This workshop is aimed at and designed to provide a better exposure for faculty in the verification of digital circuits using front-end tools with hands on Lab Sessions . FDP mainly intends at familiarising the faculties with knowledge that are crucial for guiding students headed for semiconductor career.
About Key Resource Person
Sivakumar PR(Founder and CEO of Aceic Design Technologies)
Sivakumar is a seasoned engineering professional who has worked in various fields, including electrical engineering, academia and semiconductor industries for more than 18 years.
To know more about SivaKumar, please visit : LinkedIn:linkedin.com/in/sivapr
Workshop Agenda
• ASIC Verification Methodologies
• System Verilog HVL
• Verification Planning and Management
• UVM - Universal Verification Methodology
• Current & future trends in Semiconductor Industry
• Labs - Memory Design
• Case Study - AHB UVC
What one gains?
• Technical know-how on Functional Verification
• Enhanced classroom delivery
• Aid for research in VLSI / FPGA technology
• Hands on experience with lab session
• Platform for interaction among academicians and industry experts to discuss about the recent trends, developments, challenges and academic research activities in the field of VLSI.
Key take away:
1) Course Kit
2) FDP Certificate
3) Working Lunch, Tea & Snacks
Registration
Registration Fee includes FDP Kit, Lunch & Refreshments and participation in all programmes related to the FDP.
The details of registration fee are as follows:
Early Bird Registration Registration
Rs. 3,000/- Rs. 5,000/-
Early Bird Offer applicable up-to 30th June,2016!
Kindly contact us for group discounts for 2 or more faculties joining from same college.
How to apply?
Step 1: Faculty members from Institutes affiliated to various Universities are encouraged to Register On-line for Workshop.
👉CLICK HERE TO REGISTER ON-LINE :http://goo.gl/forms/gmy0nwj2NWdEGETp2
Step 2: After your on-line registration please wait for our call for confirmation. You will be provided with a Registration E-mail, on receipt of which you can make the registration payment as stated in the Registration E- Mail.
Step 3: E-mail us the details of Payment made and await for our Confirmation Mail.
Selection Criteria
Selection of participants will be done on ‘First Come First Serve Basis’. Organizing committee’s decision will be final in selecting the participants.
Selected candidates should bring Official ID Card, failing which they will not be eligible to attend the workshop.
We look forward to welcoming you!!
In case of any ambiguities please feel free to call us on 080-49565395 / 9901278009 , or mail us to priyanka@maven-silicon.com/ vimala@maven-silicon.com
Maven Silicon, Bangalore is organizing a Faculty Development Program (FDP) on “Functional Verification” in collaboration with Aceic Design Technologies on 3rd and 4th,September 2016.
This workshop will give the participants an invaluable resource for those who are trying to gain insight about the current needs in the VLSI industry with Key Sessions delivered by non other than Mr. Sivakumar PR- Founder and CEO of Aceic Design Technologies. This workshop is aimed at and designed to provide a better exposure for faculty in the verification of digital circuits using front-end tools with hands on Lab Sessions . FDP mainly intends at familiarising the faculties with knowledge that are crucial for guiding students headed for semiconductor career.
About Key Resource Person
Sivakumar PR(Founder and CEO of Aceic Design Technologies)
Sivakumar is a seasoned engineering professional who has worked in various fields, including electrical engineering, academia and semiconductor industries for more than 18 years.
To know more about SivaKumar, please visit : LinkedIn:linkedin.com/in/sivapr
Workshop Agenda
• ASIC Verification Methodologies
• System Verilog HVL
• Verification Planning and Management
• UVM - Universal Verification Methodology
• Current & future trends in Semiconductor Industry
• Labs - Memory Design
• Case Study - AHB UVC
What one gains?
• Technical know-how on Functional Verification
• Enhanced classroom delivery
• Aid for research in VLSI / FPGA technology
• Hands on experience with lab session
• Platform for interaction among academicians and industry experts to discuss about the recent trends, developments, challenges and academic research activities in the field of VLSI.
Key take away:
1) Course Kit
2) FDP Certificate
3) Working Lunch, Tea & Snacks
Registration
Registration Fee includes FDP Kit, Lunch & Refreshments and participation in all programmes related to the FDP.
The details of registration fee are as follows:
Early Bird Registration Registration
Rs. 3,000/- Rs. 5,000/-
Early Bird Offer applicable up-to 30th June,2016!
Kindly contact us for group discounts for 2 or more faculties joining from same college.
How to apply?
Step 1: Faculty members from Institutes affiliated to various Universities are encouraged to Register On-line for Workshop.
👉CLICK HERE TO REGISTER ON-LINE :http://goo.gl/forms/gmy0nwj2NWdEGETp2
Step 2: After your on-line registration please wait for our call for confirmation. You will be provided with a Registration E-mail, on receipt of which you can make the registration payment as stated in the Registration E- Mail.
Step 3: E-mail us the details of Payment made and await for our Confirmation Mail.
Selection Criteria
Selection of participants will be done on ‘First Come First Serve Basis’. Organizing committee’s decision will be final in selecting the participants.
Selected candidates should bring Official ID Card, failing which they will not be eligible to attend the workshop.
We look forward to welcoming you!!
In case of any ambiguities please feel free to call us on 080-49565395 / 9901278009 , or mail us to priyanka@maven-silicon.com/ vimala@maven-silicon.com
Who Can Participate?
Faculties of Electronics and communication department
Accommodation Details:
No accommodation.
Other Details:
Contact Details:
In case of any ambiguities please feel free to call us on 080-49565395 / 9901278009 , or mail us to priyanka@maven-silicon.com/
vimala@maven-silicon.com
For any clarification about
this event, please contact the above mentioned address.
Workshop
Notification 2016 :: 2 Days FDP in VLSI Technology, Bangalore-2016-Maven
silicon Softech Pvt Ltd-Bangalore-Karnataka-India
See Also