College/University/Organization
Name: St. Joseph’s Institute of Technology
Organizing Department: Department of Electronics & Communication Engineering
Event Date: 09/15/2016 -- 09/16/2016
(MM/DD/YYYY)
Last Date: 09/04/2016 (MM/DD/YYYY)
Address: Chennai, Tamilnadu, India
Registration Fee:
Rs.750
Event Website / Brochure link:
http://www.stjosephstechnology.ac.in/web/uploads/circulars/2016_2017/Worksop_ECE_Imageprocessing.pdf
Email Address: stjosephscoreel2016@gmail.com
About Event:
This workshop focuses on hands on experience in the field of
Xilinx VIVADO System.
FPGA implementation for DSP & Image, Video processing.
Physical layer Design.
Optimization Techniques.
Xilinx VIVADO System.
FPGA implementation for DSP & Image, Video processing.
Physical layer Design.
Optimization Techniques.
Who Can Participate?
Eligibility: Academicians, Research Scholars and PG students.
Accommodation Details:
Yes
Other Details:
Contact Details:
9445836031, 9944987555
For any clarification about
this event, please contact the above mentioned address.
Real Time
Signal & Image Processing Using
Xilinx VIVADO system generator and Simulation of physical layer in
communication-2016-St. Joseph’s Institute of Technology-Chennai-Tamilnadu-India
See Also